Many of today's microprocessors (referred to as “processors” herein) support a protocol in which the computer system interrupt controller is split between the processor and one or more external interrupt controllers. The portion included in the processor is typically referred to as a “local” interrupt controller and the portions maintained in external devices are typically referred to as “input/output” interrupt controllers. These interrupt controllers may support both level-triggered and edge-triggered interrupt signaling. In addition, some external devices may be capable of delivering edge-triggered or level-triggered interrupt indications to the processor's local interrupt controller without any intervening external input/output interrupt controller.
When a level-triggered interrupt signal is delivered from the input/output interrupt controller to the local interrupt controller, the interrupt remains pending in the input/output interrupt controller until an explicit acknowledgement is received from the processor. However, when edge-triggered interrupt signaling is used, the input/output interrupt controller does not need to “remember” that the interrupt is pending because with edge-triggered interrupt signaling the processor does not acknowledge the interrupt.
Edge-triggered interrupt signaling has some advantages over level-triggered interrupts. The primary advantage is that the processor can avoid the acknowledge cycles and status reads that are required with level-triggered interrupts, thus improving overall system performance.
Edge-triggered interrupts cause a problem, however, in the area of power management. In particular, if an edge-triggered interrupt is delivered from the input/output interrupt controller to the local interrupt controller at about the same time that the processor is entering a low-power state, the interrupt will not be serviced (because the processor is not currently executing instructions due to the low power state) and the processor will remain in the low power state because the system's power management logic has no knowledge that an interrupt is pending (the input/output interrupt controller does not “remember” the pending edge-triggered interrupts). Thus, the interrupt remains pending and unserviced until the power management logic causes the processor to enter a high power state due to some other system event. This latency that results from edge-triggered interrupts arriving at the processor at about the same time the processor is entering a low power state results in lower overall system performance and lost interrupts that may result in functional failures.
A separate problem occurs when a level-triggered interrupt is directly delivered by a peripheral to the processor without any visibility to the input/output interrupt controller, or if another input/output interrupt controller is used that does not have a connection to the power management logic. As with the edge-triggered case described above, the power management logic has no mechanism to detect the pending interrupt in the CPU. The processor may remain in a low power state for too long, resulting in lower overall system performance, lost interrupts, and functional failures.